In recent years, with reduction in feature sizes of semiconductor processes, there has been a trend toward further increase of the number of SRAM macros embedded in a system LSI (Large Scale Integration circuit). However, due to reduction in feature sizes of SRAMs, effect of a variation in threshold voltages (Vt) of SRAM memory cell transistors increases, thereby causing a problem in that malfunction of SRAMs occur at a voltage less than or equal to about 1 V. Therefore, for system LSIs in 45-nm and 32-nm generations or later, it is suggested to use a stabilized voltage of 1.2 V as the supply voltage for SRAM memory cells, utilizing power supply circuits, thereby to ensure operating margins of SRAMs.
In Non-Patent Document 1, a power supply CVDD generates a generated voltage stabilized at 1.2 V using a voltage regulator, is used as the power supply for an SRAM memory cell. Typically, normal operation is guaranteed for a logic circuit while the supply voltage falls within a voltage range of 1.2 V±about 10%, i.e., within a range from 1.08 V to 1.32 V. Thus, as with the configuration described in the above document, a logic circuit can operate also at a higher voltage than 1.08 V by using a stabilized voltage of 1.2 V generated within an LSI, thereby ensuring an operating margin even in an SRAM with a reduced feature size.